1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a configuration of a memory cell of a static random access memory (SRAM).
2. Description of the Background Art
Random access memories (RAMs) which are memory devices capable of arbitrarily writing, holding and reading data are mainly divided into a dynamic RAM (DRAM: Dynamic Random Access Memory) which requires a refresh operation to hold stored data and a static RAM (SRAM: Static Random Access Memory) which does not require a refresh operation.
SRAM is characterized in that although the structure thereof is more complicated than DRAM and cost per unit capacity is high than that of DRAM, high rate data read and write operations can be performed because of no need to perform a refresh operation. Due to this, SRAM is employed as, for example, a cache memory or the like which requires following up the rate of a high rate CPU (Central Processing Unit). Recently, in particular, SRAM is widely used for a portable terminal equipment or the like which operates by a battery with relatively low power consumption.
FIG. 5 is a circuit diagram showing one example of the configuration of an SRAM memory cell. In FIG. 5, a so-called CMOS (Complementary Metal Oxide Semiconductor) memory cell which consists of six MOS transistors is shown.
Referring to FIG. 5, pMOS transistors PT1 and PT2 and nMOS transistors NT1 and NT2 form two CMOS inverters to hold the signal levels of storage nodes N1 and N2 and a CMOS flip-flop circuit is constituted by cross-coupling the two CMOS inverters. To write and read data to and from storage nodes N1 and N2, access transistors NT3 and NT4 are turned on in response to the activation of a word line WL (to H level), whereby storage nodes N1 and N2 are electrically connected to bit lines BL and /BL, respectively.
If word line WL is deactivated (to L level) and access transistors NT3 and NT4 are turned off, either nMOS transistor or the pMOS transistor is turned on in each CMOS inverter in accordance with the level of the data stored in corresponding storage node N1 or N2. As a result, one of storage nodes N1 and N2 is connected to one of a power supply voltage VCC corresponding to the xe2x80x9cHxe2x80x9d level of the data and a ground voltage GND corresponding to the xe2x80x9cLxe2x80x9d level of the data and the other storage node is connected to the other voltage VCC or GND in accordance with the level of the data held in the memory cell. It is, therefore, possible to hold the data in the memory cell in a stand-by state without periodically turning on word line WL and executing a refresh operation.
FIG. 6 is a circuit diagram showing one example of another configuration of an SRAM memory cell. In FIG. 6, a so-called p-type TFT (Thin Film Transistor) load type memory cell which consists of four MOS transistors and two p-type thin film transistors PPT1 and PPT2 is shown. Thin film transistors PPT1 and PPT2 indicate transistors of a conductive type P each formed out of a polysilicon thin film.
Referring to FIG. 6, nMOS transistors NT1 and NT2 hold the signal levels of storage nodes N1 and N2, respectively. Thin film transistors PPT1 and PPT2 are connected in parallel between power supply voltage VCC and storage node N1 and node N2, respectively. It is noted that nMOS transistors NT1 and NT2 will be also referred to as xe2x80x9cdriver transistorsxe2x80x9d. Thin film transistors PPT1 and PPT2 and nMOS transistors NT1 and NT2 constitute a flip-flop circuit. To write and read data to and from storage nodes N1 and N2, access transistors NT3 and NT4 are turned on in response to the activation of word line WL (to H level), whereby storage nodes N1 and N2 are electrically connected to bit lines BL and /BL, respectively. The data write and read operations of the p-type TFT load SRAM memory cell are the same as those of the CMOS memory cell stated above. A multilayer structure can be adopted as the cell structure of this p-type TFT load SRAM memory cell. That is, it is possible to form thin film transistors PPT1 and PPT2 on a different layer from that of driver transistors NT1 and NT2 on a semiconductor substrate. Therefore, p-type TFT load SRAM memory cell has an advantage in that a cell area is small.
FIG. 7 is a circuit diagram showing one example of yet another configuration of an SRAM memory cell. In FIG. 7, a so-called high resistance load memory cell which consists of four MOS transistors and two high resistances R1 and R2 is shown.
Referring to FIG. 7, this high resistance load memory cell differs from the memory cell shown in FIG. 6 in that thin film transistors PPT1 and PPT2 are replaced by high resistances R1 and R2, respectively. It is noted that high resistances R1 and R2 and driver transistors NT1 and NT2 constitute a so-called high resistance load type flip-flop circuit. The other operations and the like of the high resistance load memory cell are the same as those of the CMOS memory cell stated above. A multilayer structure can be adopted as the cell structure of this high resistance load memory cell as in the case of the p-type TFT load memory cell. That is, it is possible to form high resistances R1 and R2 on a different layer from that of driver transistors NT1 and NT2 on a semiconductor substrate and to make the cell area small.
As one of the indicators for the operating stability of an SRAM memory cell, a static noise margin is employed.
FIG. 8 is a conceptual view showing the relationship of the static noise margin when the CMOS memory cell is in a stand-by state. As shown in FIG. 8, the input/output characteristic of the CMOS memory cell is indicated by the characteristic view of two cross-coupled inverters.
In case of FIG. 8, the characteristic curve k1 of one CMOS inverter is given. By inverting characteristic curve k1 symmetrically about a line, indicated by a dotted line in FIG. 8, having 45 degrees with respect to vertical and horizontal axes, a characteristic curve k2 is obtained. This characteristic curve k2 corresponds to the characteristic curve of the other CMOS inverter cross-coupled to one CMOS inverter stated above. A combination of characteristic curves k1 and k2 corresponds to the input/output characteristic view of the CMOS memory cell. In this case, as shown in FIG. 8, a region surrounded by curves k1 and k2 and normally referred to as xe2x80x9ccell""s eyexe2x80x9d is formed. The maximum distance L1 between curves k1 and k2 in the region corresponds to a static noise margin. It is indicated that if the distance is larger, the input/output characteristic of the CMOS memory cell is more stable.
Points S1 and S2 shown in FIG. 8 are stable points. Stable point S1 corresponds to a state in which data xe2x80x9c0xe2x80x9d is stored. Stable point S2 corresponds to a state in which data xe2x80x9c1xe2x80x9d is stored. In addition, a point S3 is a metastable point. Even if the operation of the CMOS memory cell corresponds to point S3 in an initial state, it never fails to be moved to either point S1 or S2 whenever microscopic noise occurs and is stabilized at the moved point.
On the other hand, the input/output characteristic view of the CMOS memory cell when data is read from the cell changes as shown in FIG. 9. As already stated above, when data is read from the memory cell, access transistors NT3 and NT4 are both turned on and storage nodes N1 and N2 are electrically connected to bit lines BL and /BL, respectively. As a result, the so-called cell""s eye, i.e., the static noise margin becomes very narrow during data read as shown in FIG. 9. If the so-called cell""s eye disappears, it is difficult to hold the data.
It is said that the area of above-stated p type TFT load memory cell can be made smaller than that of the CMOS memory cell, which area is about eight times as large as that of a DRAM memory cell if manufactured under the same design standard (design rule). This is because the p type thin film transistors can be formed on a layer above the nMOS transistors. However, the ratio of an ON current to an OFF current driven by the driver transistors is far lower than that of the CMOS memory cell. For example, while the ratio of the ON current and the OFF current of the p-type TFT load memory cell is several hundreds and that the ratio of the CMOS memory cell is not less than several hundred thousands. Due to this, the static noise margin of the p-type TFT load memory cell is narrower than that of the CMOS memory cell in a stand-by state. Further, if the memory cell is made smaller in size, the ratio of the ON current and the OFF current becomes lower. Besides, if the power supply voltage is lower, the ratio becomes lower, as well. As a result, it is difficult to secure this static noise margin particularly when data is read from the memory cell.
In addition, the area of the high resistance load memory cell can be made smaller than that of the CMOS memory cell since the high resistances can be formed on a layer above the nMOS transistors as in the case of the p-type TFT load memory cell. However, because of the arrangement of the high resistances (passive elements) between the storage nodes and the power supply voltage, respectively, a stand-by current is always penetrated into one of the storage nodes by the driver transistors. The high resistance load memory cell has, therefore, a disadvantage in that a stand-by current is high on an entire chip. Furthermore, the static noise margin of the high resistance load memory cell is narrower than that of the CMOS memory cell in a stand-by state.
Accordingly, various memories have both advantages and disadvantages. At present, therefore, CMOS memory cells having a relatively wide static noise margin are normally employed.
Nevertheless, since the configuration of the CMOS memory cell is such that six transistors are formed on a semiconductor substrate and both an N well and a P well are provided as well structures for forming the transistors in one memory cell, the area of one memory cell is very large. It is normally said that such a CMOS memory cell has an area about twelfth times as large as that of a DRAM memory cell if manufactured under the same design standard (design rule).
Furthermore, a relatively wide static noise margin can be secured for this CMOS memory cell, compared with those of the p-type TFT load memory cell and the high resistance load memory cell in a stand-by state. However, during data read, even the static noise margin of the CMOS memory cell becomes narrow as shown in FIG. 9. It is noted that the static noise margins of the other p-type TFT load memory cell and high resistance load memory cell become far narrower than that of the CMOS memory cell.
It is an object of the present invention to provide a semiconductor memory device having memory cells each of which has a relatively small area and which has high operating stability.
In short, the present invention provides a semiconductor memory device which includes a plurality of memory cells, a plurality of word lines, a plurality of bit lines and a plurality of write select lines.
A plurality of memory cells are arranged in a matrix. A plurality of word lines are provided to correspond to memory cell rows, respectively, and selectively activated in accordance with a row select result. A plurality of bit lines are provided to correspond to memory cell columns, and transmitting data, respectively. A plurality of write select lines are provided to correspond to the memory cell columns, respectively, and selectively activated during data write. In addition, each of the plurality of memory cells includes a flip-flop circuit and first to third switch circuits. The flip-flop circuit sets one storage node of first and second storage nodes at one voltage of first and second voltages and the other storage node at the other voltage in accordance with the stored data. The first switch circuit electrically couples the corresponding bit line to an internal node in accordance with activation of the word line corresponding to the selected memory cell during data read and the data write. The second switch circuit electrically couples a predetermined one storage node of the first and second storage node to the internal node in accordance with the activation of the write select line corresponding to the selected memory cell during the data write. The third switch circuit electrically couples the internal node to the first voltage in accordance with a voltage level of the predetermined one storage node during the data read.
Therefore, a main advantage of the present invention is in that during data read, the internal node is electrically coupled to the first voltage in accordance with a predetermined one of the first and second storage node and the voltage of this internal node is transmitted to the corresponding bit line. That is, since the data read can be executed without electrically coupling the bit line to the storage node, it is possible to secure the static noise margin of a memory cell during the data read and to execute a stable read operation.